RITENBR=DEBUG_HAS_NO_EFFECT_, RITENCLR=THE_TIMER_WILL_NOT_B, RITINT=THE_COUNTER_VALUE_DO, RITEN=TIMER_DISABLED_
Control register.
| RITINT | Interrupt flag 0 (THE_COUNTER_VALUE_DO): The counter value does not equal the masked compare value. 1 (THIS_BIT_IS_SET_TO_1): This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. |
| RITENCLR | Timer enable clear 0 (THE_TIMER_WILL_NOT_B): The timer will not be cleared to 0. 1 (THE_TIMER_WILL_BE_CL): The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. |
| RITENBR | Timer enable for debug 0 (DEBUG_HAS_NO_EFFECT_): Debug has no effect on the timer operation. 1 (THE_TIMER_IS_HALTED_): The timer is halted when the processor is halted for debugging. |
| RITEN | Timer enable. 0 (TIMER_DISABLED_): Timer disabled. 1 (TIMER_ENABLED_THIS_): Timer enabled. This can be overruled by a debug halt if enabled in bit 2. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |